1. Field of the Invention
This invention relates generally to analysis tools used in the processes for the manufacture of semiconductor devices. More specifically, this invention relates to determining the sensitivity of the scan tools used in the manufacture of semiconductor devices. Even more specifically, this invention relates to a method of manufacturing calibration wafers to determine the sensitivity of scan tools used in the manufacture of semiconductor devices.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect or defects increases the cost of the remaining usable chips because the cost of manufacturing the wafer must be apportioned to the number of good chips that can be sold to consumers.
A single semiconductor chip can require numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits.
After many of these process steps, the wafer is placed in a scan tool that detects defects. As the semiconductor devices have become smaller, the size of defects that are or can be "killer" defects has also become smaller. Because of this, it has become increasingly important and critical that the smaller size defects can be accurately detected. However, it has been found that each scan tool has a different sensitivity (calibration) at the lower end, that is, each scan tool can "just" detect different size defects.
Therefore, what is needed is an accurate method of determining the sensitivity of each scan tool in order to determine the smallest size of defects that the scan tool can accurately detect.